1. Field of the Invention
The invention generally relates to circuits and methods for built-in self tests (BISTs).
2. Description of the Related Art
Intra-system digital data transmission techniques over backplanes and other transmission mediums have migrated from the use of relatively wide data busses with many data lines to the use of high-speed serial links with relatively few data lines. The serial approach can provide the same or greater aggregate bandwidth while simplifying the backplane design by eliminating a great deal of routing congestion and the need for trace length matching.
For example, as illustrated in FIG. 1, a common implementation uses a serializer 102 at the transmit end of a link to convert “wide” or parallel bus data into high-speed serial data, and uses a deserializer 104, at the receive end of the link to convert back to “wide” or parallel bus data for further processing. For full-duplex operation with unidirectional links, both serializer and deserializer operations can be provided at both ends of the backplane, and fully integrated serializer/deserializer (SerDes) devices are widely available from many integrated circuit (IC) vendors.
While simplifying some aspects of board or backplane design, the conversion to serial data transmission introduces significant signal integrity challenges. In some instances, data rates have approached or even exceeded the physical bandwidth limitations of backplane materials and construction methods.
FIG. 2 illustrates examples of transfer functions of backplanes intended for high-speed digital data transmission. A horizontal axis 202 indicates frequency, with increasing frequency to the right. A ratio of voltage magnitude is indicated along a vertical axis 204. The transfer function of a transmission medium, such as a backplane, can adversely affect the quality of a signal carried therein. When the highest frequency component of the transmitted signal exceeds the bandwidth of the transmission medium, one readily observable result is signal distortion resulting in a reduced sampling window (known as the valid data “eye”) at the receiver as illustrated by FIG. 3A and FIG. 3B.
A data eye corresponds to superimposed waveforms for binary bits of “0” and “1” within a bit period. FIG. 3A illustrates an example of a data eye corresponding to a relatively undistorted transmitted signal. FIG. 3B illustrates an example of a data eye for a transmitted signal that has been distorted by high frequency attenuation. For example, a backplane of limited bandwidth can induce the type of distortion observable in the data eye of FIG. 3B.
Present techniques to ameliorate the disadvantages of relatively low-bandwidth backplanes are inadequate. For example, the transmission medium itself can be changed to increase the roll-off frequency. This typically involves redesigning backplanes to take advantage of recent developments in materials that permit higher bandwidth transmission lines to be formed. Unfortunately, aside from the costs of redesigning boards, these new materials are significantly more expensive to use during manufacture, increasing cost of the overall system. In addition, the availability of high-performance high-bandwidth materials may not be able to keep pace with increases in demand for even higher data signaling rates in the future, so that a redesign of backplanes may not provide a dependable solution.
Another approach is to configure a SerDes transmitter to “pre-distort” the signal in a fashion that is notionally the inverse or complement of the distortion induced by the backplane. Thus, when the two effects are combined, the result presented to the receiver can closely approximate the originally-intended signal. A typical transmitter predistortion is to boost the high-frequency components of the signal, emphasizing the transitions in the data more than the logic-valid regions. This is commonly referred to as “pre-emphasis” of the data signal. The amount of pre-emphasis should be adjusted to match the characteristics of the intended transmission medium, so that making this feature programmable allows a given device to be used in a variety of systems.
Another approach is to configure the SerDes receiver to be better able to accommodate the reduced data eye opening. In this approach, some sort of front-end “equalization” is provided to the SerDes receiver so that the receiver includes a filter that approximates the inverse frequency response of the backplane. For example, a finite impulse response filter (FIR) can be used as an equalization circuit. Thus, the high-frequency components of the transmitted signal are first attenuated by the backplane, then boosted back up by the equalizer, prior to being sampled by the receiver. Once again, in order to be used in a variety of systems, a device will often incorporate some sort of programmability in its equalizer.
The demand for high-performance SerDes devices, particularly those including some form of pre-emphasis and/or equalization, is creating a unique challenge for integrated circuit (IC) vendors. While the underlying data communication protocols are fundamentally digital, the speed and waveform shaping capabilities use advanced analog design practices. Such “mixed-signal” ICs are typically challenging to test economically for a variety of reasons.
For purely digital devices, it is often sufficient to simply verify that all of the components and interconnects have been well formed, i.e., the device is structurally intact, without undue emphasis on functional performance. The fundamental components in purely digital circuits are operated in a region where they are relatively insensitive to small perturbations such as parametric variations in manufacturing. Such methods as scan-based automated test pattern generation (ATPG) are relatively simple and satisfactory methods for efficiently testing purely digital ICs.
High speed serializer/deserializer transceivers (SerDes) in general, and pre-emphasis and equalization in particular, are typically implemented with complicated analog or mixed-signal circuits. SerDes and other high-performance analog and mixed-signal devices are infrequently amenable to such techniques due to their relatively high sensitivity to small perturbations. Such circuits have proven to be impervious to systematic design-for-test (DFT) techniques, and adequate production test coverage is normally only possible with full-rate functional testing. In addition, it should be noted that the insertion of test structures itself may impact performance of the circuit to the point of preventing functionality. Furthermore, relatively small parametric variations in manufacturing, or passive defects that might not impact the performance of digital circuits, can cause catastrophic degradation in sensitive analog circuits.
One trustworthy method for reliably testing the very high-speed logic used on the serial side of a SerDes transceiver is to test the SerDes transceiver functionally at or beyond the rated performance of the device. This, however, is often not easily accomplished. Available automated test equipment (ATE) for IC production testing has been lagging the data rates of SerDes devices for the past several years such that the automated equipment that would be desirable in a production environment is often not available. This trend can be expected to continue provided that SerDes technology advances at approximately the same pace (or faster) than ATE technology.
Solutions with external SerDes test equipment wired into ATE fixtures, or fixture-mounted ATE channel multiplexing circuitry have been developed, but these solutions are clumsy and expensive, and are also inaccurate, unreliable, and do not scale to multi-link devices. Augmenting ATE equipment with external equipment such as bit error rate testers (BERTs) can serve as a workaround, but very quickly becomes prohibitively expensive and impossible to implement reliably for high link-count devices. For example, a 64-channel differential transceiver would use 64 BERT testers cabled together into the ATE test head, as well as include at least 256 high bandwidth single-pole double-throw relays on the test fixture for switching in ATE channels for DC parametric testing. The cost of the BERTs alone would dwarf even the most expensive digital ATE platforms currently commercially available, and experience has shown that the test fixture and cabling would be impractical to maintain during high volume manufacturing.
Another solution is to use loopback or loop-around testing, where the transmitter is either externally or internally connected to the receiver in test mode and used to provide functional data at-speed. For devices that incorporate a phase locked loop (PLL) that can frequency multiply a lower speed reference clock, and that also include on-board data generation and bit-error monitoring, this can provide significant test coverage with greatly reduced ATE performance.
Conventional loopback testing techniques have many limitations that can still result in a relatively high test escape rate. For example, a relatively good transmitter can compensate for a defective receiver, or vice-versa. In another example, programmable pre-emphasis and equalization parameters cannot be measured or stressed effectively with a fixed loopback transmission path. In some cases, operation using pre-emphasis and equalization is not even possible as a relatively short loopback path used for testing will typically have too high a bandwidth, resulting in over-compensated signals. Conversely, when the bandwidth of the loopback path is restricted, operation without pre-emphasis and equalization is not practical. Since many new SerDes devices support multiple pre-emphasis and equalization modes, at least some modes can disadvantageously remain incompletely tested by conventional tests, which risks missing the detection of failures.
For further background, see Fiedler, et al, A 1.0625 Gbps Transceiver with 2×-Oversampling and Transmit Signal Pre-Emphasis, 1997 IEEE International Solid-State Circuit Conference Digest of Technical Papers, pp. 238-239; Gagnon, Kaminska, Optical Communication Channel Test Using BIST Approaches, IEEE International Test Conference Proceedings 1997, pp. 626-635; and Laquai, et al., Testing Gigabit Multilane SerDes Interfaces with Passive Jitter Injection Filters, IEEE International Test Conference Proceedings 2001, pp. 297-304. Also see U.S. Pat. No. 5,386,590 to Dolan; U.S. Pat. No. 6,397,042 to Prentice, et al.; and U.S. Pat. No. 6,571,393 to Ko, et al, the disclosures of which are hereby incorporated by reference in their entireties.